Invention Grant
US09577674B2 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same
有权
具有长度为64800和码率为2/15和16符号映射的低密度奇偶校验码字的位交织器，以及使用相同位的比特交织方法
- Patent Title: Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same
- Patent Title (中): 具有长度为64800和码率为2/15和16符号映射的低密度奇偶校验码字的位交织器，以及使用相同位的比特交织方法
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Application No.: US14626169Application Date: 2015-02-19
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Publication No.: US09577674B2Publication Date: 2017-02-21
- Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
- Applicant: Electronics and Telecommunications Research Institute
- Applicant Address: KR Daejeon
- Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee Address: KR Daejeon
- Priority: KR10-2015-0021505 20150212
- Main IPC: H03M13/11
- IPC: H03M13/11 ; H03M13/25 ; H03M13/27
Abstract:
A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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