Invention Grant
- Patent Title: Self aligned patterning with multiple resist layers
- Patent Title (中): 具有多个抗蚀剂层的自对准图案化
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Application No.: US14753523Application Date: 2015-06-29
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Publication No.: US09581900B2Publication Date: 2017-02-28
- Inventor: Ming-Feng Shieh , Chih-Ming Lai , Ken-Hsien Hsieh , Ru-Gun Liu , Shih-Ming Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G03F7/20
- IPC: G03F7/20 ; G03F7/00 ; H01L21/033 ; G03F7/40

Abstract:
A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate.
Public/Granted literature
- US20150301447A1 Self Aligned Patterning With Multiple Resist Layers Public/Granted day:2015-10-22
Information query
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