A semiconductor memory device is provided which includes memory cells, a first error correction code (ECC) circuit configured to generate at least one selected parity bit corresponding to a selected data bit using an error correction code during a write operation and to correct an error of the selected data bit using the selected parity bit during a read operation, and a test circuit configured to selectively perform at least one of an error correction operation and a redundancy repair operation on at least one of the selected data bit and the selected parity bit based on test mode register set (TMRS) information.