Invention Grant
- Patent Title: Semiconductor die package including low stress configuration
- Patent Title (中): 半导体芯片封装包括低应力配置
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Application No.: US13324078Application Date: 2011-12-13
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Publication No.: US09583454B2Publication Date: 2017-02-28
- Inventor: Maria Clemens Y. Quinones , Maria Cristina B. Estacio
- Applicant: Maria Clemens Y. Quinones , Maria Cristina B. Estacio
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H01L21/60
- IPC: H01L21/60 ; H01L23/00 ; H01L23/31 ; H01L23/433 ; H01L23/495

Abstract:
A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.
Public/Granted literature
- US20120083071A1 SEMICONDUCTOR DIE PACKAGE INCLUDING LOW STRESS CONFIGURATION Public/Granted day:2012-04-05
Information query
IPC分类: