Invention Grant
- Patent Title: Multilevel memory stack structure and methods of manufacturing the same
- Patent Title (中): 多层内存堆栈结构及其制造方法相同
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Application No.: US14972389Application Date: 2015-12-17
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Publication No.: US09583500B2Publication Date: 2017-02-28
- Inventor: Jayavel Pachamuthu , Johann Alsmeier , Henry Chien
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L27/00
- IPC: H01L27/00 ; H01L27/115 ; H01L29/792 ; H01L27/06 ; H01L21/822 ; H01L27/24

Abstract:
A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.
Public/Granted literature
- US20160104715A1 MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME Public/Granted day:2016-04-14
Information query
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