Invention Grant
US09583602B2 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs
有权
用于CMOS架构的隧道场效应晶体管(TFET)和制造N型和P型TFET的方法
- Patent Title: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs
- Patent Title (中): 用于CMOS架构的隧道场效应晶体管(TFET)和制造N型和P型TFET的方法
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Application No.: US15209552Application Date: 2016-07-13
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Publication No.: US09583602B2Publication Date: 2017-02-28
- Inventor: Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
- Applicant: Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/739 ; H01L29/16 ; H01L29/161 ; H01L29/06 ; H01L29/24 ; H01L29/267 ; H01L27/092 ; H01L29/04 ; H01L29/10 ; H01L29/165 ; H01L29/20 ; H01L29/423 ; H01L29/786

Abstract:
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
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