Invention Grant
US09588566B2 Programmable time delay and signal polarity improving transceiver signal-to-noise metric
有权
可编程的时间延迟和信号极性提高收发器信噪比度量
- Patent Title: Programmable time delay and signal polarity improving transceiver signal-to-noise metric
- Patent Title (中): 可编程的时间延迟和信号极性提高收发器信噪比度量
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Application No.: US13226503Application Date: 2011-09-07
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Publication No.: US09588566B2Publication Date: 2017-03-07
- Inventor: Jaiganesh Balakrishnan , Sriram Murali
- Applicant: Jaiganesh Balakrishnan , Sriram Murali
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: H04B15/00
- IPC: H04B15/00 ; G06F1/30 ; H04H40/72

Abstract:
Suppression of interference across transceivers integrated on a single semiconductor chip. An example of a method of reducing noise in a transceiver includes introducing an adjustable time delay into a signal between a first section of a signal path into which noise may be introduced and a second section of the signal path into which noise may be introduced. The method also includes selectively adjusting the time delay and signal polarity to improve a signal-to-noise metric of the transceiver. An example of the transceiver includes a transmitter and a receiver. The transceiver also includes an adjustable time delay between a first section of a transceiver signal path into which noise may be introduced and a second section of the transceiver signal path into which noise may be introduced and circuitry for reducing noise by adjusting a value of the time delay.
Public/Granted literature
- US20130058490A1 SUPPRESSION OF INTERFERENCE ACROSS TRANSCEIVERS INTEGRATED ON A SINGLE SEMICONDUCTOR CHIP Public/Granted day:2013-03-07
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