Invention Grant
- Patent Title: Memory controller and decoding method
- Patent Title (中): 内存控制器和解码方式
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Application No.: US14743061Application Date: 2015-06-18
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Publication No.: US09588772B2Publication Date: 2017-03-07
- Inventor: Daiki Watanabe , Daisuke Fujiwara , Ryo Yamaki
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H03M13/03
- IPC: H03M13/03 ; G06F9/30

Abstract:
According to one embodiment, a memory controller includes a decoder configured to perform approximate maximum likelihood decoding, the decoder including: an initial value generation unit configured to calculate first data on the basis of a received word read from a non-volatile memory; a storage unit configured to store the first data and a predetermined number of second data; an update unit configured to calculate new second data by using the predetermined number of second data stored and update the storage unit; an arithmetic unit configured to output an addition result of the first data and the latest second data as decoded word information; and a selection unit configured to select a decoded word with the maximum likelihood on the basis of a plurality of the decoded word information.
Public/Granted literature
- US20160246603A1 MEMORY CONTROLLER AND DECODING METHOD Public/Granted day:2016-08-25
Information query
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