A memory device and method for altering a performance characteristic of a memory array to increase a rate at which the memory device writes data in response to the memory device experiencing a demand for bandwidth above a threshold. The memory device may include a memory controller and a memory array, which may include memristive memory elements. To alter a performance characteristic, for example, the memristive memory elements may be written at sub-full resistive states which have a smaller difference between high and low resistive states, and/or the memory controller may disable a subset of memory elements and/or memory cells along a bit line and/or word line of the memory array. The subset of memory elements may be re-enable in response to the demand for bandwidth falling below the threshold, and data may be moved and/or rearranged within the memory device when the subset of memory elements is re-enabled. Altering the performance characteristic may increase a rate at which the memory device writes data.