An amorphous silicon gate driving circuit includes multiple cascaded shift registers. Each of the shift registers includes a shift register unit, which contains multiple TFTs and multiple capacitors, an N-th output terminal GN, an (N+1)-th output terminal GN+1, a high voltage signal terminal Vgh and a low voltage signal terminal Vgl; and an output control unit having an N-th additional output terminal. The output control unit is configured to control a time period during which the N-th additional output terminal outputs a high voltage level to be within a time period during which the N-th output terminal outputs the high voltage level, where a signal falling edge for turning off TFTs at a former one of two adjacent rows of pixel units is completely separated from a signal rising edge for turning on TFTs at a latter one.