Invention Grant
US09589807B1 Method for eliminating interlayer dielectric dishing and controlling gate height uniformity
有权
消除层间电介质凹陷和控制栅极高度均匀性的方法
- Patent Title: Method for eliminating interlayer dielectric dishing and controlling gate height uniformity
- Patent Title (中): 消除层间电介质凹陷和控制栅极高度均匀性的方法
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Application No.: US15164146Application Date: 2016-05-25
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Publication No.: US09589807B1Publication Date: 2017-03-07
- Inventor: Haigou Huang , Jinping Liu , Huang Liu , Yuanfang Lu
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/283
- IPC: H01L21/283 ; H01L21/762 ; H01L21/3213 ; H01L29/66
Abstract:
A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.
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