Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US14274289Application Date: 2014-05-09
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Publication No.: US09589840B2Publication Date: 2017-03-07
- Inventor: Chin-Li Kao , Chang-Chi Lee , Yi-Shao Lai
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Priority: TW102116464A 20130509
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L23/367 ; H01L23/525 ; H01L23/532 ; H01L23/13 ; H01L23/14 ; H01L23/498 ; H01L21/48 ; H01L23/00

Abstract:
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.
Public/Granted literature
- US20140332957A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2014-11-13
Information query
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