Invention Grant
US09589840B2 Semiconductor package and manufacturing method thereof 有权
半导体封装及其制造方法

Semiconductor package and manufacturing method thereof
Abstract:
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.
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