Invention Grant
- Patent Title: Device having multiple-layer pins in memory MUX1 layout
- Patent Title (中): 在存储器MUX1布局中具有多层引脚的器件
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Application No.: US14835788Application Date: 2015-08-26
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Publication No.: US09589885B2Publication Date: 2017-03-07
- Inventor: Hung-Jen Liao , Jung-Hsuan Chen , Chien Chi Tien , Ching-Wei Wu , Jui-Che Tsai , Hong-Chen Cheng , Chung-Hsing Wang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW
- Agency: Hauptman Ham, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/50 ; H01L27/11 ; H01L23/532 ; H01L27/02 ; H01L23/528 ; H01L23/498 ; H01L23/522
Abstract:
An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.
Public/Granted literature
- US20150364412A1 DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT Public/Granted day:2015-12-17
Information query
IPC分类:
