Invention Grant
- Patent Title: Device architecture and method for precision enhancement of vertical semiconductor devices
- Patent Title (中): 用于垂直半导体器件精密增强的器件架构和方法
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Application No.: US14816911Application Date: 2015-08-03
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Publication No.: US09589889B2Publication Date: 2017-03-07
- Inventor: Thomas E. Harrington, III
- Applicant: D3 Semiconductor LLC
- Applicant Address: US TX Addison
- Assignee: D3 SEMICONDUCTOR LLC
- Current Assignee: D3 SEMICONDUCTOR LLC
- Current Assignee Address: US TX Addison
- Agency: Schultz & Associates, P.C.
- Main IPC: H01L23/525
- IPC: H01L23/525 ; H01L27/112 ; H01L29/78 ; H01L21/66 ; H01L29/739 ; H01L49/02 ; H01L29/66 ; H01L27/088

Abstract:
Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability. Device parametrics are trimmed to improve a single device, or a parametric specification is targeted to match specifications on two or more devices.
Public/Granted literature
- US20150340318A1 DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICAL SEMICONDUCTOR DEVICES Public/Granted day:2015-11-26
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