Invention Grant
- Patent Title: Method for interconnect scheme
- Patent Title (中): 互连方案
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Application No.: US14803671Application Date: 2015-07-20
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Publication No.: US09589890B2Publication Date: 2017-03-07
- Inventor: Hsin-Chieh Yao , Carlos H. Diaz , Cheng-Hsiung Tsai , Chung-Ju Lee , Chien-Hua Huang , Hsi-Wen Tien , Shau-Lin Shue , Tien-I Bao , Yung-Hsu Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L21/3213
Abstract:
A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.
Public/Granted literature
- US20170025346A1 Method for Interconnect Scheme Public/Granted day:2017-01-26
Information query
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