Invention Grant
US09589899B2 Semiconductor device having a gate cutting region and a cross-coupling pattern between gate structures
有权
具有栅极切割区域和栅极结构之间的交叉耦合图案的半导体器件
- Patent Title: Semiconductor device having a gate cutting region and a cross-coupling pattern between gate structures
- Patent Title (中): 具有栅极切割区域和栅极结构之间的交叉耦合图案的半导体器件
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Application No.: US14801937Application Date: 2015-07-17
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Publication No.: US09589899B2Publication Date: 2017-03-07
- Inventor: Hwi-Chan Jun , Dae-Hee Weon , Heon-Jong Shin , Yu-Sun Lee
- Applicant: Hwi-Chan Jun , Dae-Hee Weon , Heon-Jong Shin , Yu-Sun Lee
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2014-0136531 20141010
- Main IPC: H01L23/535
- IPC: H01L23/535 ; H01L27/02 ; H01L29/423 ; H01L27/088 ; H01L21/8234

Abstract:
In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.
Public/Granted literature
- US20160104678A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME Public/Granted day:2016-04-14
Information query
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