Invention Grant
US09594562B2 Extensible execution unit interface architecture with multiple decode logic and multiple execution units
有权
具有多个解码逻辑和多个执行单元的可扩展执行单元接口架构
- Patent Title: Extensible execution unit interface architecture with multiple decode logic and multiple execution units
- Patent Title (中): 具有多个解码逻辑和多个执行单元的可扩展执行单元接口架构
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Application No.: US15095799Application Date: 2016-04-11
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Publication No.: US09594562B2Publication Date: 2017-03-14
- Inventor: Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Middleton Reutlinger
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38

Abstract:
Various circuit arrangements tightly couple together decode logic associated with multiple types of execution units and having varying priorities to enable instructions that are decoded as valid instructions for multiple types of execution units to be forwarded to a highest priority type of execution unit among the multiple types of execution units. Among other benefits, when an auxiliary execution unit is coupled to a general purpose processing core with the decode logic for the auxiliary execution unit tightly coupled with the decode logic for the general purpose processing core, the auxiliary execution unit may be used to effectively overlay new functionality for an existing instruction that is normally executed by the general purpose processing core, e.g., to patch a design flaw in the general purpose processing core or to provide improved performance for specialized applications.
Public/Granted literature
- US20160224342A1 EXTENSIBLE EXECUTION UNIT INTERFACE ARCHITECTURE WITH MULTIPLE DECODE LOGIC AND MULTIPLE EXECUTION UNITS Public/Granted day:2016-08-04
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