Invention Grant
- Patent Title: Method for checking and fixing double-patterning layout
- Patent Title (中): 双图案布局的检查和固定方法
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Application No.: US13681094Application Date: 2012-11-19
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Publication No.: US09594866B2Publication Date: 2017-03-14
- Inventor: Dio Wang , Ken-Hsien Hsieh , Huang-Yu Chen , Li-Chun Tien , Ru-Gun Liu , Lee-Chung Lu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW
- Agency: Hauptman Ham, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/00 ; G21K5/00

Abstract:
A method includes receiving layout data representing a plurality of patterns. The layout data includes a plurality of layers and spaces identified between adjacent patterns. In at least one layer of the plurality of layers, the adjacent patterns violate a G0-rule. The method further includes determining whether each identified space is a critical G0-space. The identified space is determined to be a critical G0-space if a portion of at least one adjacent pattern that is removed merges two adjacent odd-loops of G0-spaces into a single even loop or G0 spaces or alternatively, if a portion of an adjacent pattern that is removed converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of at least one adjacent pattern and updating a spacing of a layer that is adjacent to the layers within the adjacent pattern that violate the G0-rule.
Public/Granted literature
- US20130080980A1 METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT Public/Granted day:2013-03-28
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