Invention Grant
- Patent Title: Chip package method and package assembly
- Patent Title (中): 芯片封装方法和封装组装
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Application No.: US15179284Application Date: 2016-06-10
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Publication No.: US09595453B2Publication Date: 2017-03-14
- Inventor: Xiaochun Tan , Jiaming Ye
- Applicant: Silergy Semiconductor Technology (Hangzhou) Ltd.
- Applicant Address: CN Hangzhou
- Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
- Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
- Current Assignee Address: CN Hangzhou
- Agency: Westman, Champlin & Koehler, P.A.
- Priority: CN201510317651 20150611
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/48 ; H01L21/56 ; H01L23/495 ; H01L23/31

Abstract:
The present disclosure relates to a chip package method and a package assembly. A metal plate is micro-etched to form trenches having a predetermined depth. A metallic conductor is formed as a leadframe by filling the trenches with a material having relatively small adhesion with the metal plate. In such manner, the metal plate can be peeled off from a package body after the chip is electrically coupled to the metallic conductor and encapsulated by a molding process. A bottom of the metallic conductor is exposed from the package body. A chip package is thus completed. It simplifies a manufacture process for forming a chip package, reduces manufacture cost, and increases reliability of the chip package.
Public/Granted literature
- US20160365257A1 CHIP PACKAGE METHOD AND PACKAGE ASSEMBLY Public/Granted day:2016-12-15
Information query
IPC分类: