Invention Grant
US09595529B2 Fuse cell circuit, fuse cell array and memory device including the same 有权
保险丝盒电路,保险丝盒阵列和包含相同的存储器件

Fuse cell circuit, fuse cell array and memory device including the same
Abstract:
A fuse cell circuit may include a bit line, a first fuse transistor having first and second program states, a first select transistor coupled between one terminal of the first fuse transistor and the bit line, and suitable for turning on when the first fuse transistor is selected, a second fuse transistor including one terminal coupled to the other terminal of the first fuse transistor, and having first and second program states, and a second select transistor coupled between a other terminal of the second fuse transistor and the bit line, and suitable for turning on when the second fuse transistor is selected.
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