Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain

Invention Grant

US09595597B1 Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain 有权

Title translation: 半导体器件包括嵌入式SiGe源极/漏极的双间隔物和均匀的外延缓冲层界面

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Patent Title: Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain
Patent Title (中): 半导体器件包括嵌入式SiGe源极/漏极的双间隔物和均匀的外延缓冲层界面
Application No.: US14951660

Application Date: 2015-11-25
Publication No.: US09595597B1

Publication Date: 2017-03-14
Inventor: Veeraraghavan S. Basker , Zuoguang Liu , Tenko Yamashita , Chun-Chen Yeh
Applicant: International Business Machines Corporation
Applicant Address: US NY Armonk
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Current Assignee Address: US NY Armonk
Agency: Cantor Colburn LLP
Agent Vazken Alexanian
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L29/66 ; H01L21/3065 ; H01L21/02

Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain

Abstract:

A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The semiconductor fin includes a channel region formed of a first semiconductor material interposed between opposing embedded source/drain regions formed of a second semiconductor material different from the first semiconductor material. At least one gate stack is formed on the upper surface of the semiconductor substrate and wraps around the channel region. The embedded source/drain regions have a symmetrical shape and a uniform embedded interface.

Abstract(Chinese):

半导体器件包括在半导体衬底的上表面上的至少一个半导体鳍片。半导体鳍片包括由插入在与第一半导体材料不同的第二半导体材料形成的相对的嵌入式源极/漏极区域之间的第一半导体材料形成的沟道区域。在半导体衬底的上表面上形成至少一个栅极堆叠并且缠绕在沟道区域周围。嵌入式源极/漏极区域具有对称形状和均匀的嵌入式接口。

Public/Granted literature

US20170062588A1 SEMICONDUCTOR DEVICE INCLUDING DUAL SPACER AND UNIFORM EPITAXIAL BUFFER INTERFACE OF EMBEDDED SIGE SOURCE/DRAIN Public/Granted day:2017-03-02

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺