Invention Grant
- Patent Title: Testing device for validating stacked semiconductor devices
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Application No.: US13629273Application Date: 2012-09-27
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Publication No.: US09599661B2Publication Date: 2017-03-21
- Inventor: Timothy D. Wig
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G01R31/28

Abstract:
Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. By utilizing HDI substrates, embodiments of the invention enable “breaking out” the signal pins on multiple layers, perhaps double or triple the routing layers of the package channel; however, the geometry of the transmission lines and other factors may be chosen to ensure channel parameters such as impedance and crosstalk closely emulate the final device package.
Public/Granted literature
- US20140084954A1 TESTING DEVICE FOR VALIDATING STACKED SEMICONDUCTOR DEVICES Public/Granted day:2014-03-27
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