A floating-point arithmetic device of an embodiment includes: a first functional unit configured to receive first input data to execute first arithmetic operation in a first rounding mode; a second functional unit configured to receive second input data to execute second arithmetic operation in a second rounding mode; a first output circuit capable of selectively outputting a first output or a first arithmetic operation result of the first arithmetic operation, the first output obtained by halving a first value obtained by adding a second arithmetic operation result of the second arithmetic operation to the first arithmetic operation result; and a second output circuit capable of selectively outputting a second output or the second arithmetic operation result, the second output obtained by halving a second value obtained by subtracting the second arithmetic operation result from the first arithmetic operation result.