A system for allocating field programmable gate array (FPGA) resources, comprises a plurality of FPGAs operable to implement one or more pipeline circuits; and one or more processors operable to determine the size of a set of data to be processed, determine an amount of time available to process the data set, determine an operational clock speed for the plurality of FPGAs, determine, based at least in part on the determined size of the set of data, the determined amount of time, and the determined operational clock speed, a number of FPGAs to allocate to process the set of data within the determined amount of time, and allocate at least the determined number of the plurality of FPGAs to process the set of data.