Invention Grant
- Patent Title: Method and apparatus for debugging HDL design code and test program code
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Application No.: US14527298Application Date: 2014-10-29
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Publication No.: US09600398B2Publication Date: 2017-03-21
- Inventor: Bindesh Patel , I-Liang Lin , Ming-Hui Hsieh , Jien-Shen Tsai
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Alston & Bird LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F11/36 ; G06F17/50

Abstract:
Disclosed is a method of debugging a simulation system including design code representing a design of an electronic circuit and test program code configured to exercise the design code. The method includes using an interactive debugging tool to execute an interactive simulation of the test program code and the design code, and, during the interactive simulation, displaying, using the interactive debugging tool, information of a simulation results file storing a plurality of signal values generated by executing the test program code and the design code during a previously executed simulation.
Public/Granted literature
- US20150121346A1 METHOD AND APPARATUS FOR DEBUGGING HDL DESIGN CODE AND TEST PROGRAM CODE Public/Granted day:2015-04-30
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