Invention Grant
- Patent Title: Apparatus and method for implementing a multi-level memory hierarchy
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Application No.: US13997189Application Date: 2011-09-30
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Publication No.: US09600416B2Publication Date: 2017-03-21
- Inventor: Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
- Applicant: Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2011/054430 WO 20110930
- International Announcement: WO2013/048497 WO 20130404
- Main IPC: G06F13/12
- IPC: G06F13/12 ; G06F13/38 ; G06F12/08 ; G11C11/406 ; G11C14/00

Abstract:
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”
Public/Granted literature
- US20140129767A1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY Public/Granted day:2014-05-08
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