Invention Grant
- Patent Title: Repeater insertions providing reduced routing perturbation caused by flip-flop insertions
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Application No.: US14664680Application Date: 2015-03-20
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Publication No.: US09600620B2Publication Date: 2017-03-21
- Inventor: Daman Ahluwalia , Nikhil Jayakumar
- Applicant: Xpliant
- Applicant Address: US CA San Jose
- Assignee: XPLIANT
- Current Assignee: XPLIANT
- Current Assignee Address: US CA San Jose
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
System and method of automatically performing repeater insertions in physical design of an integrated circuit. Repeaters are inserted in interconnects in a staggered fashion and spaced apart to accommodate potential flip-flop insertions. The sufficient spacing between the repeaters in combination with the staggered pattern ensures that flip-flop insertions can be performed at any of the repeater locations without space limitation. When rerouting is needed following a flip-flop insertion on an interconnect, automatic rerouting is performed but restricted to a short and specified region along the interconnect. Thereby, the resulted alteration from the current routing configuration is minimal and deterministic.
Public/Granted literature
- US20160275230A1 REPEATER INSERTIONS PROVIDING REDUCED ROUTING PERTURBATION CAUSED BY FLIP-FLOP INSERTIONS Public/Granted day:2016-09-22
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