• Patent Title: Repeater insertions providing reduced routing perturbation caused by flip-flop insertions
  • Application No.: US14664680
    Application Date: 2015-03-20
  • Publication No.: US09600620B2
    Publication Date: 2017-03-21
  • Inventor: Daman AhluwaliaNikhil Jayakumar
  • Applicant: Xpliant
  • Applicant Address: US CA San Jose
  • Assignee: XPLIANT
  • Current Assignee: XPLIANT
  • Current Assignee Address: US CA San Jose
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Repeater insertions providing reduced routing perturbation caused by flip-flop insertions
Abstract:
System and method of automatically performing repeater insertions in physical design of an integrated circuit. Repeaters are inserted in interconnects in a staggered fashion and spaced apart to accommodate potential flip-flop insertions. The sufficient spacing between the repeaters in combination with the staggered pattern ensures that flip-flop insertions can be performed at any of the repeater locations without space limitation. When rerouting is needed following a flip-flop insertion on an interconnect, automatic rerouting is performed but restricted to a short and specified region along the interconnect. Thereby, the resulted alteration from the current routing configuration is minimal and deterministic.
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