Invention Grant
- Patent Title: Apparatus and method decoupling visibility bins and render tile dimensions for tiled rendering
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Application No.: US14570710Application Date: 2014-12-15
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Publication No.: US09600926B2Publication Date: 2017-03-21
- Inventor: Peter L. Doyle
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T15/40 ; G06T1/20

Abstract:
An apparatus and method are described for decoupling visibility bins and render tile dimensions for tiled rendering. In one embodiment of the invention, a single visibility pass over the scene objects is performed and all the visibility bins are generated in parallel. This allows for high performance when the number of render tiles exceeds the number of visibility bins. The regions upon which visibility testing/recording is done is decoupled from the render tile regions in one embodiment of the invention. This allows a given visibility bin to map to multiple render tiles, thus allowing a fixed number of visibility bins to support any number of render tiles.
Public/Granted literature
- US20160171751A1 Decoupling Visibility Bins and Render Tile Dimensions for Tiled Rendering Public/Granted day:2016-06-16
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |