Invention Grant
- Patent Title: Memory system and control method
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Application No.: US14481437Application Date: 2014-09-09
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Publication No.: US09601197B2Publication Date: 2017-03-21
- Inventor: Takahiro Nango , Shingo Akita
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G11C14/00
- IPC: G11C14/00 ; G11C7/20 ; G11C5/14 ; G11C11/417

Abstract:
According to one embodiment, there is provided a memory system including a volatile memory and a controller. The volatile memory has 1st to Kth memory banks (K is a natural number equal to or larger than 2) that are kept in a power-on state and (K+1)th to Nthmemory banks (N is a natural number larger than K) whose power state is changed. The power state is the power-on state or a power-down state. The controller performs wake-up operation for the (K+1)th to Nth memory banks in parallel with access operation to the 1st to Kth memory banks. The wake-up operation changes the power state from the power-down state to the power-on state.
Public/Granted literature
- US20150255149A1 MEMORY SYSTEM AND CONTROL METHOD Public/Granted day:2015-09-10
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