Invention Grant
- Patent Title: Dummy metal gate structures to reduce dishing during chemical-mechanical polishing
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Application No.: US14959786Application Date: 2015-12-04
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Publication No.: US09601489B2Publication Date: 2017-03-21
- Inventor: Chan-Hong Chern , Chih-Chang Lin , Julie Tran , Jacklyn Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/092 ; H01L21/321 ; H01L29/423 ; H01L21/8238

Abstract:
The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
Public/Granted literature
- US20160086949A1 Dummy Metal Gate Structures to Reduce Dishing During Chemical-Mechanical Polishing Public/Granted day:2016-03-24
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