Invention Grant
- Patent Title: Lut cascading circuit
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Application No.: US14852164Application Date: 2015-09-11
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Publication No.: US09602108B1Publication Date: 2017-03-21
- Inventor: Brian C. Gaide , Steven P. Young , Alireza S. Kaviani
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Robert Brush
- Main IPC: H03K19/173
- IPC: H03K19/173 ; H03K19/177 ; H03K19/00

Abstract:
In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.
Information query
IPC分类: