Invention Grant
- Patent Title: Delay locked loop (DLL) locked to a programmable phase
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Application No.: US14841267Application Date: 2015-08-31
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Publication No.: US09602111B1Publication Date: 2017-03-21
- Inventor: Chun-Ju Shen , Jenn-Gang Chern
- Applicant: SK hynix memory solutions inc.
- Applicant Address: US CA San Jose
- Assignee: SK hynix memory solutions Inc.
- Current Assignee: SK hynix memory solutions Inc.
- Current Assignee Address: US CA San Jose
- Agency: IP & T Group LLP
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/081 ; H03L7/02 ; H03K19/21

Abstract:
An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.
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