Invention Grant
- Patent Title: Technologies for high-speed PCS supporting FEC block synchronization with alignment markers
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Application No.: US14580737Application Date: 2014-12-23
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Publication No.: US09602401B2Publication Date: 2017-03-21
- Inventor: Adee O. Ran , Kent C. Lusted
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: H03M13/03
- IPC: H03M13/03 ; H04L12/721 ; H04L1/00 ; H03M13/25

Abstract:
Technologies for high-speed data transmission include a network port logic having one or more communication lanes coupled to a forward error correction (FEC) sublayer and a physical coding sublayer (PCS). To transmit data, the PCS encodes the data to be transmitted into encoded data blocks using a 66 b/64 b line code and inserts alignment marker blocks after every 16,383 encoded data blocks. The FEC encodes the encoded data blocks into 80-block FEC codewords starting at a predefined offset from an alignment marker. Thus, each alignment marker is at one of five predefined offsets from the beginning of an FEC codeword. Each alignment marker may include a unique block type field usable with FEC encoding. The PCS may include one or more logical lanes, each operating at 25 Gb/s. Embodiments of the network port logic may include a single PCS lane or sixteen PCS lanes. Other embodiments are described and claimed.
Public/Granted literature
- US20160087753A1 TECHNOLOGIES FOR HIGH-SPEED PCS SUPPORTING FEC BLOCK SYNCHRONIZATION WITH ALIGNMENT MARKERS Public/Granted day:2016-03-24
Information query
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