Invention Grant
- Patent Title: Trie stage balancing for network address lookup
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Application No.: US14108581Application Date: 2013-12-17
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Publication No.: US09602407B2Publication Date: 2017-03-21
- Inventor: Zixiong Wang
- Applicant: Futurewei Technologies, Inc.
- Applicant Address: CN Shenzhen
- Assignee: Huawei Technologies Co., Ltd.
- Current Assignee: Huawei Technologies Co., Ltd.
- Current Assignee Address: CN Shenzhen
- Agency: Conley Rose, P.C.
- Main IPC: H04L12/44
- IPC: H04L12/44 ; H04L12/745 ; H04L12/743 ; H04L12/56

Abstract:
A trie comprising a plurality of subtries may be balanced by storing, in a first memory stage, a first root that identifies a first subtrie of a trie and a second root that identifies a second subtrie, which is a direct or indirect child of the first subtrie. A plurality of network address prefixes representing vertexes in the plurality of subtries may be stored in at least one additional memory stage. As the first subtrie is located on a top subtrie level which may contain relatively fewer network address prefixes, promoting the second subtrie to the top subtrie level may help improve memory utilization. Further, looking up any received network address may have less memory access latency.
Public/Granted literature
- US20150172191A1 Trie Stage Balancing for Network Address Lookup Public/Granted day:2015-06-18
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