Invention Grant
- Patent Title: Capacitance measurement circuit and method
-
Application No.: US14132722Application Date: 2013-12-18
-
Publication No.: US09606155B2Publication Date: 2017-03-28
- Inventor: Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
- Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: G01R27/26
- IPC: G01R27/26 ; G01R31/28

Abstract:
A circuit includes a stacked circuit layer, a plurality of test contact points, and a comparator. The stacked circuit layer includes a plurality of reference capacitors each having a reference capacitance. Each of the test contact points is electrically connecting to an under-test capacitor of an under-test module. The comparator compares the reference capacitance of one of the reference capacitors with an under-test capacitance of the under-test capacitor corresponding to one of the test contact points to measure a range of the under-test capacitance.
Public/Granted literature
- US20150168459A1 Capacitance Measurement Circuit And Method Public/Granted day:2015-06-18
Information query