Invention Grant
- Patent Title: VLIW processor, instruction structure, and instruction execution method
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Application No.: US14989647Application Date: 2016-01-06
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Publication No.: US09606798B2Publication Date: 2017-03-28
- Inventor: Yuki Kobayashi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2011-262706 20111130
- Main IPC: G06F9/00
- IPC: G06F9/00 ; G06F9/44 ; G06F9/30 ; G06F9/38
Abstract:
A processor, includes a first comparison operation unit; a second comparison operation unit; a first operation unit; a second operation unit; a third operation unit; and a register, wherein the first comparison operation unit receives a first comparison operation signal, a first input signal, and a second input signal, performs a comparison operation indicated by the first comparison operation signal on the first input signal and the second input signal, and outputs a result of the comparison operation, the second comparison operation unit receives a second comparison operation signal, a third input signal, and a fourth input signal, performs a comparison operation indicated by the second comparison operation signal on the third input signal and the fourth input signal, and outputs a result of the comparison operation, the first operation unit receives the comparison result of the first comparison operation unit.
Public/Granted literature
- US20160117168A1 VLIW PROCESSOR, INSTRUCTION STRUCTURE, AND INSTRUCTION EXECUTION METHOD Public/Granted day:2016-04-28
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