Invention Grant
- Patent Title: Methods of dividing layouts and methods of manufacturing semiconductor devices using the same
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Application No.: US14261299Application Date: 2014-04-24
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Publication No.: US09607852B2Publication Date: 2017-03-28
- Inventor: Jeong-Hoon Lee , Sang-Wook Seo , Hye-Soo Shin
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2013-0079502 20130708
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/469 ; H01L21/311 ; G03F7/20 ; H01L21/027 ; H01L21/3213 ; H01L21/768
Abstract:
Target pattern layouts that include lower and upper target patterns are designed. Each lower target pattern is combined with a upper target pattern that at least partially overlaps a top surface thereof to form combination structures. The combination structures are divided into first and second combination structures. A first target pattern is formed from the lower target pattern in the first combination structure and a third target pattern is formed from the upper target pattern in the first combination structure. The first and third target patterns are formed in first and third lithography processes, respectively. A second target pattern is formed from the lower target pattern in the second combination structure and a fourth target pattern is formed from the upper target pattern in the second combination structure. The second and fourth target patterns are formed in second and fourth lithography processes, respectively.
Public/Granted literature
- US20150011022A1 METHODS OF DIVIDING LAYOUTS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME Public/Granted day:2015-01-08
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