Provided is a MOSFET, comprising: a substrate (100); a gate stack (500) on the substrate (100); source/drain regions (305) in the substrate on both sides of the gate stack (500); an interlayer dielectric layer (400) covering the source/drain regions; and source/drain extension regions (205) under edges on both sides of the gate stack (500); wherein insulators, which are not connected each other, are formed beneath the source/drain extension regions (205) under edges on both sides of the gate stack (500). By means of the MOSFET in the present disclosure, negative effects induced by DIBL on device performance can be effectively reduced.