Invention Grant
- Patent Title: Delay lock loop
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Application No.: US14967899Application Date: 2015-12-14
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Publication No.: US09608642B1Publication Date: 2017-03-28
- Inventor: Qiang Si , Fan Jiang
- Applicant: VIA Alliance Semiconductor Co., Ltd.
- Applicant Address: CN Shanghai
- Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee Address: CN Shanghai
- Agency: McClure, Qualey & Rodack, LLP
- Priority: CN201510875427 20151202
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/085 ; H03K5/134 ; H03K5/00

Abstract:
A delay lock loop including a selection unit, a delay unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit is coupled to the selection unit. The delay unit includes a delay factor and delays the first clock signal to generate a third clock signal according to the delay factor. The phase detection unit is coupled to the delay unit and the selection unit and generates the indication signal according to a phase difference between the second and third clock signals. The delay unit adjusts the delay factor according to the indication signal.
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