Invention Grant
- Patent Title: Delay lock loop
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Application No.: US14967932Application Date: 2015-12-14
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Publication No.: US09608643B1Publication Date: 2017-03-28
- Inventor: Qiang Si , Fan Jiang
- Applicant: VIA Alliance Semiconductor Co., Ltd.
- Applicant Address: CN Shanghai
- Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee Address: CN Shanghai
- Agency: McClure, Qualey & Rodack, LLP
- Priority: CN201510875141 20151202
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/085 ; H03K5/134 ; H03K5/00

Abstract:
A delay lock loop is provided. A delay unit delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit delays a third clock signal to generate a fourth clock signal. A phase detection unit generates an indication signal according to a phase difference between the second and fourth clock signals. When a duration of the indication signal being at a first level does not arrive at a pre-determined value and the indication signal is at a second level, the control unit increases the delay factor. When the duration of the indication signal being at the first level arrives at the pre-determined value and the indication signal is at the second level, the control unit reduces the delay factor.
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