An A/D conversion circuit includes: a reference signal generation section that includes an integrator circuit having a first constant current source and generates a reference signal that changes in accordance with a constant current output by the first constant current source; a comparison section that executes a comparison process between an analog signal and the reference signal and terminates the comparison process; a clock generation section that includes a delay section having delay units for delaying an input signal for a predetermined time and outputting delayed input signals in accordance with a constant current output by a second constant current source, and outputs a lower phase signal based on the signals output from the delay units; a latch section that latches the lower phase signal at a timing related to the termination of the comparison process; and a count section that counts a clock based on the lower phase signal.