Invention Grant
- Patent Title: Testing memory devices with parallel processing operations
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Application No.: US14191289Application Date: 2014-02-26
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Publication No.: US09612272B2Publication Date: 2017-04-04
- Inventor: Xinguo Zhang , Michael Jones , Ken Hanh Duc Lai , Edmundo De La Puente , Alan S. Krech, Jr.
- Applicant: Advantest Corporation
- Applicant Address: JP Tokyo
- Assignee: ADVANTEST CORPORATION
- Current Assignee: ADVANTEST CORPORATION
- Current Assignee Address: JP Tokyo
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G11C29/56

Abstract:
An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.
Public/Granted literature
- US20150243369A1 TESTING MEMORY DEVICES WITH PARALLEL PROCESSING OPERATIONS Public/Granted day:2015-08-27
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