- Patent Title: System and method for functional verification of multi-die 3D ICs
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Application No.: US14595251Application Date: 2015-01-13
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Publication No.: US09612277B2Publication Date: 2017-04-04
- Inventor: Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G01R31/28 ; G01R31/3185

Abstract:
A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
Public/Granted literature
- US20150123699A1 SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs Public/Granted day:2015-05-07
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