Invention Grant
- Patent Title: MFENCE and LFENCE micro-architectural implementation method and system
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Application No.: US13619919Application Date: 2012-09-14
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Publication No.: US09612835B2Publication Date: 2017-04-04
- Inventor: Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
- Applicant: Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Vecchia Patent Agent, LLC
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F9/30 ; G06F9/40 ; G06F9/38

Abstract:
A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
Public/Granted literature
- US20130067200A1 MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM Public/Granted day:2013-03-14
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