- Patent Title: Data processor including prefix instruction selecting a flag out of a plurality of flags generated by a subsequent instruction operating on multiple operand sizes in parallel
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Application No.: US14284342Application Date: 2014-05-21
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Publication No.: US09612838B2Publication Date: 2017-04-04
- Inventor: Fumio Arakawa
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2008-037069 20080219
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
Instructions for generating flags according to operands' data sizes, and instruction sets handled by a RISC data processor including an instruction capable of executing an operation on operands in more than one data size are disclosed. An identical operation process is conducted on the small-size operand and on low-order bits of the large-size operand, and flags are generated capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation. Thus, a reduction in instruction code space of the RISC data processor can be achieved.
Public/Granted literature
- US20140258692A1 DATA PROCESSOR Public/Granted day:2014-09-11
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