Invention Grant
- Patent Title: Higher accuracy Z-culling in a tile-based architecture
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Application No.: US14061443Application Date: 2013-10-23
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Publication No.: US09612839B2Publication Date: 2017-04-04
- Inventor: Ziyad S. Hakura , Jerome F. Duluk, Jr.
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06T15/00 ; G06T15/40 ; G06T1/20 ; G06T1/60 ; G09G5/395 ; G09G5/00 ; G06T15/50 ; G06F12/0808 ; G06F12/0875 ; G06F9/44 ; G06T15/80

Abstract:
A graphics processing pipeline configured for z-cull operations. The graphics processing pipeline comprising a screen-space pipeline and a tiling unit. The screen-space pipeline includes a z-cull unit configured to perform z-culling operations. The tiling unit is configured to determine that a first set of primitives overlaps a first cache tile. The tiling unit is also configured to transmit the first set of primitives to the screen-space pipeline for processing. The tiling unit is further configured to select between processing the first set of primitives in a full-surface z-cull mode or processing the first set of primitives in a partial-surface z-cull mode. The tiling unit is also configured to cause the z-cull unit to process the first set of primitives in the full-surface z-cull mode or to process the first set of primitives in the partial-surface z-cull mode.
Public/Granted literature
- US20140118348A1 HIGHER ACCURACY Z-CULLING IN A TILE-BASED ARCHITECTURE Public/Granted day:2014-05-01
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