Invention Grant
- Patent Title: Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources
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Application No.: US13138176Application Date: 2010-01-18
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Publication No.: US09612844B2Publication Date: 2017-04-04
- Inventor: Andrew Webber
- Applicant: Andrew Webber
- Applicant Address: GB Kings Langley
- Assignee: Imagination Technologies Limited
- Current Assignee: Imagination Technologies Limited
- Current Assignee Address: GB Kings Langley
- Agency: Vorys, Sater, Seymour and Pease LLP
- Agent Vincent M DeLuca
- Priority: GB0900769.1 20090116
- International Application: PCT/GB2010/000062 WO 20100118
- International Announcement: WO2010/082032 WO 20100722
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F9/50

Abstract:
A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads (32, 34) with differing hardware resources comprising the steps of receiving a plurality of streams of instructions (38, 44) and determining which hardware threads are able to receive instructions for execution (40, 46), determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions (36) and executing the instruction in dependence on the result of the determination (50).
Public/Granted literature
- US20120124338A1 MULTI-THREADED DATA PROCESSING SYSTEM Public/Granted day:2012-05-17
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