Synchronization mechanisms for high-integrity computing
Abstract:
A system includes a first plurality of processors, a second plurality of processors dissimilar from the first plurality of processors, a first arbitration device coupled to the first plurality of processors, and a second arbitration device coupled to the second plurality of processors. The first arbitration device and the second arbitration device is configured to receive event data, store the received event data, and to output the received event data at substantially a same time. At least one processor of the first plurality of processors and at least one processor of the second plurality of processors are configured to access the event data.
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