Invention Grant
- Patent Title: Matrix transposing circuit
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Application No.: US14662246Application Date: 2015-03-19
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Publication No.: US09613669B2Publication Date: 2017-04-04
- Inventor: Chih-Hsu Yen , Fan-Di Jou
- Applicant: Industrial Technology Research Institute
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW103123490A 20140708
- Main IPC: G11C14/00
- IPC: G11C14/00 ; G11C8/04 ; G11C7/10 ; G11C19/00 ; G11C19/28 ; G11C19/38 ; G06F7/78

Abstract:
The disclosure provides a matrix transposing circuit for outputting a transposed N×N matrix. The matrix transposing circuit includes: an input resister array with m×N array; a memory having b storage blocks; an output register array with N×m array. N, m, n, b are integer in power of 2, N can be completely divided by m and n, and N=n×m×b. The matrix is divided into multiple sub-matrixes with m×n array to form Y matrix. Each of sub-matrixes is correspondingly stored to the b storage blocks. The input resister array has a first shifting direction to receive entry data and a second shifting direction to output data to the b storage blocks. The output resister array has a first shifting direction to read data from the b storage blocks and a second shifting direction to output the transposed matrix.
Public/Granted literature
- US20160012012A1 MATRIX TRANSPOSING CIRCUIT Public/Granted day:2016-01-14
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