- Patent Title: Mismatch and noise insensitive sense amplifier circuit for STT MRAM
-
Application No.: US15163268Application Date: 2016-05-24
-
Publication No.: US09613674B2Publication Date: 2017-04-04
- Inventor: John K. DeBrosse
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: G11C5/08
- IPC: G11C5/08 ; G11C11/16 ; G11C7/02 ; G11C7/06

Abstract:
A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second n-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.
Public/Granted literature
- US20160267958A1 MISMATCH AND NOISE INSENSITIVE STT MRAM Public/Granted day:2016-09-15
Information query